1. Field of the Invention
The present invention relates to the aligning of a semiconductor substrate in preparation for a semiconductor manufacturing or test process.
2. Field of the Invention
In general, a semiconductor substrate is aligned using a semiconductor alignment apparatus before the substrate is processed or tested. In particular, semiconductor alignment apparatus are typically used in a stepper or a scanner of photolithographic equipment, and in semiconductor device test equipment comprising a tester and a probe card mounted thereon. In addition, semiconductor alignment apparatus have been continuously upgraded to precisely recognize information concerning the semiconductor substrate and the chips thereon. These upgrades are in line with the overall manufacturing goal of yielding a number of good chips from the semiconductor substrate.
Photolithography is used to form a number of such chips on the semiconductor substrate by producing a series of overlapping patterns on the substrate. Thus, the substrate must be precisely aligned with the photolithographic equipment if the patterns are to be formed properly relative to one another. On the other hand, the tester tests a semiconductor device by sending electrical signals to the semiconductor chip or receiving electrical signals from the semiconductor chip through the probe card. To this end, the probe card includes a plurality of pins that are to contact respective pads on the semiconductor substrate. Therefore, the semiconductor substrate must be aligned with the tester to obtain proper contact between the semiconductor device and the probe card.
Furthermore, conventional semiconductor alignment apparatus select and use one template for aligning the semiconductor substrate in preparation for the semiconductor manufacturing or test process. The template is a pattern of high discriminating power, and can be easily found by the semiconductor alignment apparatus at one of the chips of the semiconductor substrate.
However, due to discrepancies related to their manufacturing process, those templates among the respective chips on a semiconductor substrate or among the respective semiconductor substrates may have different discriminating powers. If the semiconductor alignment apparatus picks up an image of a template having a low discriminating power in the course of an alignment process, the semiconductor substrate may be transferred back to a cassette. Thus, the manufacturing process is delayed, thereby adding to the unit cost of production.
U.S. Pat. No. 4,870,288 to Abuku et al. discloses an alignment method comprising the steps of finding a template at the region of a selected chip of a semiconductor substrate, reading the template to obtain coordinates of the location of the selected chip and of the other chips on the semiconductor substrate, and using the coordinates to align the semiconductor substrate. More specifically, the coordinates are used to derive correction values. The correction values are added to the original coordinates to adjust the location of the semiconductor substrate relative to the semiconductor device manufacturing equipment, for example. However, the accuracy of the method is highly dependent on the (template) manufacturing process or on the exterior environment because the method uses only one template. Thus, the method can be accompanied by delays and is prone to producing alignment errors.